Phase noise and jitter measurements in SEU-Hardened CMOS phase locked loop design
Document Type
Conference Proceeding
Publication Date
4-21-2021
Abstract
Single event upset (SEU) is a significant problem in analog, digital, and mixed signal circuits. The extent of the attacks increases in radiation susceptible environments such as military and aerospace. Phase locked loop (PLL) is ubiquitous and usually employed as data recovery or clock signal in some electronic devices used in these environments. Single event transient causes ionizing particles to interact with the transistor and generate more leakage current that can result in malfunctioning of the transistor. A radiation hardened PLL is proposed whereby each block is designed to be SEU tolerant. Dual and triple redundancies are employed in the design of phase-frequency detector and frequency divider, respectively. The results show that the phase-locked loop operates from 3.5 to 4 GHz with the center frequency of 3.9 GHz. The phase noise of the voltage-controlled oscillator is estimated to be -109.5 dBc/Hz at 10 MHz offset frequency and the jitter is 128 ps at 3.9 GHz.
Publication Source (Journal or Book title)
2021 IEEE International IOT, Electronics and Mechatronics Conference, IEMTRONICS 2021 - Proceedings
Recommended Citation
Adesina, N., Srivastava, A., Ullah Khan, M., & Xu, J. (2021). Phase noise and jitter measurements in SEU-Hardened CMOS phase locked loop design. 2021 IEEE International IOT, Electronics and Mechatronics Conference, IEMTRONICS 2021 - Proceedings https://doi.org/10.1109/IEMTRONICS52119.2021.9422482
