An ultra-low power MOS2tunnel field effect transistor PLL design for IoT applications
Document Type
Conference Proceeding
Publication Date
4-21-2021
Abstract
This work presents the implementation of analytical transport model of MoS2tunnel field effect transistor (TFET) using Verilog-A in Cadence/Spectre. The parameters of the model are extracted, and most notable is its high ION/IOFF ratio, which makes it suitable for low power design, and IoT applications. Subsequently, we employ the TFET model in the design of ultralow power phase locked loop (PLL). Various components of PLL are examined in terms of their structures and functions. The results show that the voltage controlled oscillator (VCO) operates from 0.5 GHz to 2.9 GHz with a tuning range of 82.8%. It also consumes 1.91 µW power at 2 GHz carrier and has a phase noise of -117.3 dBc/Hz at 1 MHz offset frequency. The average power consumed by phase locked loop is 0.021 mW. In addition, the operation of the PLL is not sensitive to temperature variations.
Publication Source (Journal or Book title)
2021 IEEE International IOT, Electronics and Mechatronics Conference, IEMTRONICS 2021 - Proceedings
Recommended Citation
Adesina, N., Srivastava, A., Ullah Khan, A., & Xu, J. (2021). An ultra-low power MOS2tunnel field effect transistor PLL design for IoT applications. 2021 IEEE International IOT, Electronics and Mechatronics Conference, IEMTRONICS 2021 - Proceedings https://doi.org/10.1109/IEMTRONICS52119.2021.9422641
