Threshold voltage analytical model for strained Si SOI MOSFET with high-k dielectric
Document Type
Article
Publication Date
11-1-2010
Abstract
A strained Si fully depleted SOI MOSFET, which has the advantages of strained Si, high-k gate and SOI structure, is presented in this paper. A two-dimensional analytical model for the threshold voltage in strained Si fully depleted SOI MOSFET with high-k dielectric is proposed by solving Possion's equation. Several important parameters are taken into account in the model. Relationships between threshold voltage, Ge Profile and thickness of strained silicon are investigated. The result shows that the threshold voltage decreases with Ge Profile and strained silicon thickness increasing. Relationships between threshold voltage, dielectric constant of high k gate and doping conceration of strained silicon are also investigated. The result shows that the threshold voltage increases with dielectric constant of high-k and doping conceration of strained silicon increasing. SCE and DIBL are analyzed finally, which also demonstrate that this novel device can suppress SCE and DIBL effect greatly. ©2010 Chin. Phys. Soc.
Publication Source (Journal or Book title)
Wuli Xuebao/Acta Physica Sinica
First Page
8131
Last Page
8136
Recommended Citation
Li, J., Liu, H., Li, B., Cao, L., & Yuan, B. (2010). Threshold voltage analytical model for strained Si SOI MOSFET with high-k dielectric. Wuli Xuebao/Acta Physica Sinica, 59 (11), 8131-8136. Retrieved from https://repository.lsu.edu/ag_exst_pubs/527