Third order CMOS decimator design for sigma delta modulators

Identifier

etd-11092009-163619

Author

Hemalatha Mekala, Louisiana State University and Agricultural and Mechanical CollegeFollow

Degree

Master of Science (MS)

Department

Electrical and Computer Engineering

Document Type

Thesis

Abstract

A third order Cascaded Integrated Comb (CIC) filter has been designed in 0.5μm n-well CMOS process to interface with a second order oversampling sigma-delta ADC modulator. The modulator was designed earlier in 0.5μm technology. The CIC filter is designed to operate with 0 to 5V supply voltages. The modulator is operated with ±2.5V supply voltage and a fixed oversampling ratio of 64. The CIC filter designed includes integrator, differentiator blocks and a dedicated clock divider circuit, which divides the input clock by 64. The CIC filter is designed to work with an ADC that operates at a maximum oversampling clock frequency of up to 25 MHz and with baseband signal bandwidth of up to 800 kHz. The design and performance of the CIC filter fabricated has been discussed.

Date

2009

Document Availability at the Time of Submission

Release the entire work immediately for access worldwide.

Recommended Citation

Mekala, Hemalatha, "Third order CMOS decimator design for sigma delta modulators" (2009). LSU Master's Theses. 858.
https://repository.lsu.edu/gradschool_theses/858

Committee Chair

Srivastava, Ashok

DOI

10.31390/gradschool_theses.858