Identifier
etd-04012006-004043
Degree
Doctor of Philosophy (PhD)
Department
Electrical and Computer Engineering
Document Type
Dissertation
Abstract
A low cost, high accuracy method is described in detail for measuring image placement in integrated circuit manufacture. The method measures both the overlay between levels and the absolute placement of features in a single level. The overlay is measured by a technique which views multiple levels separately. The absolute distances between features on a test wafer are measured by comparing the features to precision gratings. Optical imaging techniques are described for viewing and analyzing the grating images, as well as for measuring distortions in the observing microscope and a video camera. These techniques permit image placement measurements to be made to an accuracy limited by that of available gratings, at present about 2 nm. In addition they were applied to a prototype encoder system, demonstrating the potential improvement in commercial encoders by a factor of more than 100.
Date
2006
Document Availability at the Time of Submission
Release the entire work immediately for access worldwide.
Recommended Citation
Jiang, Li, "Integrated circuit metrology by multilevel patterning technology" (2006). LSU Doctoral Dissertations. 2394.
https://repository.lsu.edu/gradschool_dissertations/2394
Committee Chair
Martin Feldman
DOI
10.31390/gradschool_dissertations.2394