#### Title

IMPLEMENTATION OF A TRIANGULAR PERMUTATION NETWORK USING WAFER SCALE INTEGRATION.

#### Document Type

Conference Proceeding

#### Publication Date

12-1-1986

#### Abstract

A permutation network is investigated as a candidate for wafer scale integration (WSI). The KLW (W. Kautz, K. N. Levett, and A. Waksman, 1986) triangular permutation network has a regular structure and many local connections and is thus believed to be a good choice for WSI. The authors describe the design of the permutation network on a gate array chip, including the results of simulation runs using the Tegas simulator. Next they show how this circuit could be implemented using several different WSI schemes. The gate array chip can permute ten inputs to ten outputs, each input consisting of two bits. Based on Tegas simulations the worst-case propagation time for the signal is 85 ns.

#### First Page

269

#### Last Page

274

#### Recommended Citation

Koppelman, D., Thirumalai, A., McDonald, J., & Oruc, A. (1986). IMPLEMENTATION OF A TRIANGULAR PERMUTATION NETWORK USING WAFER SCALE INTEGRATION.., 269-274. Retrieved from https://repository.lsu.edu/eecs_pubs/662