Fault-tolerant multiple bus networks for fan-in algorithms

Document Type

Conference Proceeding

Publication Date

1-1-1996

Abstract

We consider a large class of algorithms called 'Fan-in algorithms' that are useful for problems involving semigroup operations. This paper deals with the design of fault-tolerant multiple bus networks (MBNs) suited to run Fan-in algorithms. We present two methods for constructing Fan-in MBNs with tolerance to bus faults, that have nearly optimal performance and processor fan-out. We also present a general framework that converts any Fan-in MBN (including those resilient to bus faults) into one with tolerance to processor faults, and for which faulty processors slow the original algorithm (for fault-free processors) by only one step.

Publication Source (Journal or Book title)

IEEE Symposium on Parallel and Distributed Processing - Proceedings

First Page

674

Last Page

681

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