Document Type
Conference Proceeding
Publication Date
3-1-2004
Abstract
This paper presents a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets at reducing extra off-chip memory accesses caused by interprocessor communication. This is achieved by increasing the application-wide reuse of data that resides in scratch-pad memories of processors. Our results obtained using four array-intensive image processing applications indicate that exploiting interprocessor data sharing can reduce energy-delay product significantly on a four-processor embedded system.
Publication Source (Journal or Book title)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
First Page
281
Last Page
287
Recommended Citation
Kandemir, M., Kadayif, I., Choudhary, A., Ramanujam, J., & Kolcu, I. (2004). Compiler-Directed Scratch Pad Memory Optimization for Embedded Multiprocessors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12 (3), 281-287. https://doi.org/10.1109/TVLSI.2004.824299
