Document Type
Article
Publication Date
1-1-2006
Abstract
On-chip caches consume a significant fraction of the energy in current microprocessors. As a result, architectural/circuit-level techniques such as block buffering and sub-banking have been proposed and shown to be very effective in reducing the energy consumption of on-chip caches. While there has been some work on evaluating the energy and performance impact of different block buffering schemes, we are not aware of software solutions to take advantage of on-chip cache block buffers. This article presents a compiler-based approach that modifies code and variable layout to take better advantage of block buffering. The proposed technique is aimed at a class of embedded codes that make heavy use of scalar variables. Unlike previous work that uses only storage pattern optimization or only access pattern optimization, we propose an integrated approach that uses both code restructuring (which affects the access sequence) and storage pattern optimization (which determines the storage layout of variables). We use a graph-based formulation of the problem and present a solution for determining suitable variable placements and accompanying access pattern transformations. The proposed technique has been implemented using an experimental compiler and evaluated using a set of complete programs. The experimental results demonstrate that our © 2006 ACM.
Publication Source (Journal or Book title)
ACM Transactions on Design Automation of Electronic Systems
First Page
228
Last Page
250
Recommended Citation
Kandemir, M., Ramanujam, J., & Sezer, U. (2006). Improving the energy behavior of block buffering using compiler optimizations. ACM Transactions on Design Automation of Electronic Systems, 11 (1), 228-250. https://doi.org/10.1145/1124713.1124727
