Effective automatic parallelization of stencil computations
Document Type
Conference Proceeding
Publication Date
10-30-2007
Abstract
Performance optimization of stencil computations has been widely studied in the literature, since they occur in many computationally intensive scientific and engineering applications. Compiler frameworks have also been developed that can transform sequential stencil codes for optimization of data locality and parallelism. However, loop skewing is typically required in order to tile stencil codes along the time dimension, resulting in load imbalance in pipelined parallel execution of the tiles. In this paper, we develop an approach for automatic parallelization of stencil codes, that explicitly addresses the issue of load-balanced execution of tiles. Experimental results are provided that demonstrate the effectiveness of the approach. Copyright © 2007 ACM.
Publication Source (Journal or Book title)
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)
First Page
235
Last Page
244
Recommended Citation
Krishnamoorthy, S., Baskaran, M., Bondhugula, U., Ramanujam, J., Rountev, A., & Sadayappan, P. (2007). Effective automatic parallelization of stencil computations. Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 235-244. https://doi.org/10.1145/1250734.1250761
