Title
A High Voltage-Gain GaAs Vertical Field-Effect Transistor with an InGaAs/GaAs Planar-Doped Barrier Launcher
Document Type
Article
Publication Date
1-1-1990
Abstract
A high voltage-gain GaAs vertical field-effect transistor (VFET) with an InGaAs/GaAs pseudomorphic planar-doped harrier (PDB) launcher has been demonstrated. The pseudomorphic structure which includes a small amount of indium in the launcher was grown by molecular beam epitaxy (MBE). Fabricated transistors, with good pinch-off characteristics (gate threshold voltage (Vth)= −1.6 V), have exhibited dc open-drain voltage gains up to 50 at 77 K. This high voltage gain results from the combination of high transconductances and low output conductances. The former is attributed to velocity enhancement by hot-electron injection. The latter is, in turn, attributed to the suppression of electron spillover by energy band discontinuity at the heterointerface between the launcher and the channel. © 1990 IEEE
Publication Source (Journal or Book title)
IEEE Electron Device Letters
First Page
376
Last Page
378
Recommended Citation
Won, Y., Yamasaki, K., Daniels-Race, T., Tasker, P., Schaff, W., & Eastman, L. (1990). A High Voltage-Gain GaAs Vertical Field-Effect Transistor with an InGaAs/GaAs Planar-Doped Barrier Launcher. IEEE Electron Device Letters, 11 (9), 376-378. https://doi.org/10.1109/55.62961