Leakage pressures for gasketless superhydrophobic fluid interconnects for modular lab-on-a-chip systems

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Chip-to-chip and world-to-chip fluidic interconnections are paramount to enable the passage of liquids between component chips and to/from microfluidic systems. Unfortunately, most interconnect designs add additional physical constraints to chips with each additional interconnect leading to over-constrained microfluidic systems. The competing constraints provided by multiple interconnects induce strain in the chips, creating indeterminate dead volumes and misalignment between chips that comprise the microfluidic system. A novel, gasketless superhydrophobic fluidic interconnect (GSFI) that uses capillary forces to form a liquid bridge suspended between concentric through-holes and acting as a fluid passage was investigated. The GSFI decouples the alignment between component chips from the interconnect function and the attachment of the meniscus of the liquid bridge to the edges of the holes produces negligible dead volume. This passive seal was created by patterning parallel superhydrophobic surfaces (water contact angle ≥ 150°) around concentric microfluidic ports separated by a gap. The relative position of the two polymer chips was determined by passive kinematic constraints, three spherical ball bearings seated in v-grooves. A leakage pressure model derived from the Young-Laplace equation was used to estimate the leakage pressure at failure for the liquid bridge. Injection-molded, Cyclic Olefin Copolymer (COC) chip assemblies with assembly gaps from 3 to 240 µm were used to experimentally validate the model. The maximum leakage pressure measured for the GSFI was 21.4 kPa (3.1 psig), which corresponded to a measured mean assembly gap of 3 µm, and decreased to 0.5 kPa (0.073 psig) at a mean assembly gap of 240 µm. The effect of radial misalignment on the efficacy of the gasketless seals was tested and no significant effect was observed. This may be a function of how the liquid bridges are formed during the priming of the chip, but additional research is required to test that hypothesis.

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Microsystems & nanoengineering

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