Doctor of Philosophy (PhD)


Electrical and Computer Engineering

Document Type



This work involves developing processing techniques for monolithically integrating a high-aspect-ratio microstructures with CMOS circuitry. A microsystem comprising of a microprobe array and signal processing circuitry is utilized as a test vehicle to demonstrate this fabrication process. One potential application of this microsystem is for recording neural signals from the central nervous system. The main results include thick photoresist processing, DC and pulse electroplating to form high-aspect-ratio microprobes, microprobe sharpening and developing a post-IC monolithic integration process. SU-8 is utilized for thick photoresist application. This work focuses on realization of a deep microrecess array in thick resists rather than traditional stand-alone SU-8 columns. The former encounters more processing challenges. Several novel techniques are developed including a unique development step, which results in clean microrecesses up to 450 &181;m deep with the smallest width of 40 &181;m giving aspect-ratio of 11. Electroplating is performed in nickel sulfamate electrolyte. DC plating rate is found to depend on probe location, dimension and probe spacing. Nernst diffusion boundary layer model is utilized to estimate Ni ion diffusion coefficient to be 3.3&215;10&178;-6 cm&178;2 /s. Stress in deposit is found to change from compressive to tensile with increasing DC plating current density and with increasing deposit thickness saturating respectively at 92 MPa and 73 MPa. Stress in pulse plated Ni with long pulses saturates at 54.5 MPa, while short pulse periods produce only compressive stresses between -110 MPa and -160 MPa. Surface morphology of electroplated Ni is related to built-in stress. A one-dimensional simplified model is built to describe the pulse plating process taking fixed and moving boundary approaches. The results are utilized to determine the pulse on time for plating into deep microrecesses. Nickel wire or probe is sharpened electrochemically with wires giving sharper tips under conditions of 30 &176;C, 4 V potential in a 0.5 M sulfuric acid electrolyte. Chemicals are carefully tailored in developing post-IC monolithic integration process to avoid detrimental impact on the CMOS circuitry with processing temperature maintained below 100 &176;C to avoid circuit degradation. A unique chip-level tape-and-wire bonding technique is developed to perform chip-level monolithic integration.



Document Availability at the Time of Submission

Release the entire work immediately for access worldwide.

Committee Chair

Pratul K. Ajmera