Architectural Selection for Time and Energy Considerations




Doctor of Philosophy (PhD)


Electrical and Computer Engineering

Document Type



Automatic parallelizing compilers have evolved greatly over the last decade. Tools like Pluto, Par4All and PPCG are widely adopted to generate optimized OpenMP, CUDA and OpenCL codes from input serial codes. However, in the end, it is the programmer's responsibility to select the best target architecture for a particular application depending on constraints of time or energy. In this dissertation we describe a software feature centric approach to select the architecture that will execute the fastest architecture to run a generated parallel code on between two devices attached to a heterogeneous compute node. Recognizing the importance energy aware computing is gaining, we extend our work to select the most energy efficient device to run a kernel on. We provide a software library to instrument codes for energy consumption and integrate it in the start of the art code generator, PPCG, we then apply our selection model to pick the architecture that provides the lowest energy to solution. We also analyze the relationship between execution time and energy consumption of different optimized versions of codes on Intel Xeon processors and Xeon Phi accelerator and on Nvidia Graphical processing units. To the best of our knowledge, this is the first selection models that relies strictly on software centric approach for selection and doesn't require detailed hardware models or simulators to predict code performance. Our selection accuracy is 81% in the worst case which proves that software feature centric models for selection are a reliable. This reliability combined with the ease of building these data based selection models suggests that they can eliminate the need for detailed hardware modeling for selection.



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Committee Chair

Ramanujam, Jagannathan



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