Address register allocation in digital signal processors
Document Type
Conference Proceeding
Publication Date
9-22-2008
Abstract
It is important in signal processing to optimize a code inside loops. In most programs, addressing computation accounts for a large fraction of an execution time. From the fact that typical DSP programs access massive amounts of data, it is easy to conclude that handling addressing computation properly in DSP domain is a more important subject than in general purpose computing in order to achieve a compact code with real-time performance. In this paper, we develop an algorithm that can eliminate an explicit use of address register instructions in a loop and find a lower bound on the number of ARs by finding strongly connected components (SCCs) of an extended graph. © 2008 IEEE.
Publication Source (Journal or Book title)
Proceedings of The International Conference on Embedded Software and Systems, ICESS 2008
First Page
331
Last Page
337
Recommended Citation
Hong, J., & Ramanujam, J. (2008). Address register allocation in digital signal processors. Proceedings of The International Conference on Embedded Software and Systems, ICESS 2008, 331-337. https://doi.org/10.1109/ICESS.2008.88