Storage optimization through code size reduction for digital signal processors
Document Type
Conference Proceeding
Publication Date
12-1-2008
Abstract
Most modern digital signal processors (DSPs) provide multiple address registers and a dedicated address generation unit (AGU) which performs address generation in parallel to instruction execution. There is no address computation overhead if the next address is within the auto-modify range. A careful placement of variables in memory is utilized to decrease the number of address arithmetic instructions and thus to generate compact and efficient code. The simple offset assignment (SOA) problem concerns the layout of variables for machines with one address register and the general offset assignment (GOA) deals with multiple address registers. Both these problems assume that each variable needs to be allocated for the entire duration of a program. Both SOA and GOA are NP-complete. In this paper, we present an effective heuristic for the general offset assignment problem with variable coalescing (CGOA) where two or more non-interfering variables can be mapped into the same memory location. Results on several benchmarks show the significant improvement of our solution compared to other heuristics. Results were further improved using a simulated annealing (SA). © 2008 IEEE.
Publication Source (Journal or Book title)
Proceedings of the 2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2008
First Page
107
Last Page
112
Recommended Citation
Salamy, H., & Ramanujam, J. (2008). Storage optimization through code size reduction for digital signal processors. Proceedings of the 2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2008, 107-112. https://doi.org/10.1109/ESTMED.2008.4697006