DynTile: Parametric tiled loop generation for parallel execution on multicore processors
Document Type
Conference Proceeding
Publication Date
7-1-2010
Abstract
Loop tiling is an important compiler transformation used for enhancing data locality and exploiting coarsegrained parallelism. Tiled codes in which tile sizes are runtime parameters - called parametrically-tiled codes - are important for empirical tuning systems like ATLAS. Some recent work has addressed the problem of generating sequential parametric tiled code. In this paper we describe DynTile, a system for transforming untiled sequential input C code containing affine imperfectly nested loops to parametrically tiled code for parallel execution on multicore processors. The effectiveness of the system is demonstrated using a number of benchmarks on an eight-core system. © 2010 IEEE.
Publication Source (Journal or Book title)
Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010
Recommended Citation
Hartono, A., Baskaran, M., Ramanujam, J., & Sadayappan, P. (2010). DynTile: Parametric tiled loop generation for parallel execution on multicore processors. Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010 https://doi.org/10.1109/IPDPS.2010.5470459