On the communication capability of the self-reconfigurable gate array architecture
Document Type
Conference Proceeding
Publication Date
1-1-2002
Abstract
The self-reconfigurable gate array (SRGA) architecture consists of an array of processing elements connected by row and column trees. In this paper, we study the communication capability of this interconnection fabric. We derive a necessary condition for any set of k one-to-one communications to be performed in t steps, for any 1 ≤ t ≤ k. Next we identify a property of the communication set, called partitionability, for which this necessary condition is sufficient as well. Then we show two classes of communication sets to possess this property. As a special case of one of these results, we show that the set of 1-step communications of a segmentable bus requires at most two steps on the SRGA architecture. This result implies that the communication ability of the bit model HV-R-Mesh, a special case of the bit model R-Mesh, can be emulated by the SRGA architecture without significant overhead.
Publication Source (Journal or Book title)
Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002
First Page
152
Last Page
159
Recommended Citation
El-Boghdadi, H., Vaidyanathan, R., Trahan, J., & Rai, S. (2002). On the communication capability of the self-reconfigurable gate array architecture. Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002, 152-159. https://doi.org/10.1109/IPDPS.2002.1016547