Document Type
Conference Proceeding
Publication Date
1-1-2002
Abstract
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.
Publication Source (Journal or Book title)
Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
First Page
414
Last Page
419
Recommended Citation
Ramanujam, J., Deshpande, S., Hong, J., & Kandemir, M. (2002). A heuristic for clock selection in high-level synthesis. Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, 414-419. https://doi.org/10.1109/ASPDAC.2002.994956