Document Type
Conference Proceeding
Publication Date
11-24-2009
Abstract
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing data reuse in systems with deep memory hierarchies. Tiled loops with parametric tile sizes (not compile-time constants) facilitate runtime feedback and dynamic optimizations used in iterative compilation and automatic tuning. Previous parametric multi-level tiling approaches have been restricted to perfectly nested loops, where all assignment statements are contained inside the innermost loop of a loop nest. Previous solutions to tiling for imperfect loop nests have only handled fixed tile sizes. In this paper, we present an approach to parametric multi-level tiling of imperfectly nested loops. The tiling technique generates loops that iterate over full rectangular tiles, making them amenable to compiler optimizations such as register tiling. Experimental results using a number of computational benchmarks demonstrate the effectiveness of the developed tiling approach. Copyright 2009 ACM.
Publication Source (Journal or Book title)
Proceedings of the International Conference on Supercomputing
First Page
147
Last Page
157
Recommended Citation
Hartono, A., Baskaran, M., Bastoul, C., Cohen, A., Krishnamoorthy, S., Norris, B., Ramanujam, J., & Sadayappan, P. (2009). Parametric multi-level tiling of imperfectly nested loops. Proceedings of the International Conference on Supercomputing, 147-157. https://doi.org/10.1145/1542275.1542301